Complementary metal oxide semiconductor (CMOS) devices comprising interconnected P channel and N channel metal oxide semiconductor (MOS) transistors are commonly used in the semiconductor art.
Typically, such P channel MOS (PMOS) and N channel MOS (NMOS) transistors are formed in monolithic structures on a silicon wafer, wherein devices are individually electrically isolated by the formation of reverse biased junctions in a manner known in the art. While such junction isolation suffices for a number of applications, there are certain other applications, such as those in which a "radiation hardened" structure is needed, where it is unsuitable. For effective isolation between various transistors in a radiation hardened device, it is desirable to interpose a layer of dielectric material between devices so as to obtain dielectrically isolated (DI) devices. Devices utilizing dielectric isolation are known in the art, as is described for example in U.S. Pat. No. 3,689,357 "GLASS-POLYSILICON DIELECTRIC ISOLATION" issued Sept. 5, 1972 and U.S. Pat. No. 3,938,176 "PROCESS FOR FABRICATING DIELECTRICALLY ISOLATED SEMICONDUCTOR COMPONENTS OF AN INTEGRATED CIRCUIT". However, such prior conventional techniques are expensive to implement, particularly when it is desired to effect a changeover from junction isolation to dielectric isolation. For example, if a CMOS device is being manufactured using junction isolation and it is desired to fabricate essentially the same device using dielectric isolation, an altogether different process must generally be used, requiring a different set of steps, including different masking operations with a different set of masks. Such new masks are expensive items, not only because of the precise manufacturing procedures required, but also because of the involved processes of checking and verification by proving out correct operation that are typically required before such masks can be put into service for mass production.